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Silicon Labs /EFR32MG24A020F1024IM48 /MODEM_NS /VTBLETIMING

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Interpret as VTBLETIMING

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (FRAMEDET_DELAY)VTBLETIMINGSEL 0 (VTBLETIMINGCLKSEL)VTBLETIMINGCLKSEL 0TIMINGDELAY0FLENOFF0 (DISDEMODOF)DISDEMODOF

VTBLETIMINGSEL=FRAMEDET_DELAY

Description

No Description

Fields

VTBLETIMINGSEL

Viterbi BLE timing stamp selection

0 (FRAMEDET_DELAY): Delayed frame detection will be used as Timing stamp. This mode should be selected for legacy demod and Long Range BLE demod.

1 (END_FRAME_PULSE): The end of frame detection from Narrow Viterbi demod will be used as Timing stamp. This signal is a narrow pulse signal and pulse width is one xo clock cycle.

2 (END_FRAME): The end of frame detection from Narrow Viterbi demod will be used as Timing stamp. This signal is a wdie pulse signal

3 (INV_END_FRAME): For testing only.
VTBLETIMINGCLKSEL

Viterbi BLE timing stamp clock select
TIMINGDELAY

Viterbi BLE Delay timer
FLENOFF

Timing Stamp Frame Length Offset
DISDEMODOF

Disable VT Demod Over Flow Detection

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data